Etched ran multiple rack design cycles before its chips ever arrived from fabrication

Hardware startups are accustomed to a particular rhythm: tape out the chip, wait months for fabrication, receive silicon, then begin the long process of figuring out how to cool it, house it, and deliver power to it. Etched, according to co-founder Gavin Uberti, declined to wait.

Uberti describes a design process in which rack development ran ahead of chip availability. The team used thermal chips, stand-in components that replicate the heat dissipation characteristics of production silicon without being the final product, to develop cold plates and iterate through rack configurations. By the time actual chips returned from the fabricator, the surrounding system had already been refined across multiple generations of physical design.

“We actually went through multiple iterations of the rack before the chips even came back,” Uberti said.

That sentence is worth pausing on. A rack iteration is not a software commit. It involves physical hardware: sheet metal, plumbing, thermal interface materials, power distribution, cable routing. Running multiple such iterations before the primary component exists requires both a precise thermal model of what the chip will produce and enough organizational discipline to commit real engineering time and materials to a system that cannot yet be validated end-to-end against production silicon.

We actually went through multiple iterations of the rack before the chips even came back. Gavin Uberti

The logic behind the approach is straightforward even if the execution is not. Chip fabrication at leading-edge nodes takes months. A team that waits for silicon before beginning system design is ceding that entire window. A team that models the chip’s thermal and electrical envelope accurately enough to design around it can, in principle, arrive at system readiness and chip readiness at roughly the same time. The risk is that any mismatch between the model and the actual chip forces late-stage rack redesign, which is expensive and slow.

Uberti’s account suggests Etched judged that risk acceptable, or at least preferable to the alternative of serializing the work. The use of thermal chips as proxies is the key mechanism: rather than designing against a spreadsheet model of heat output, the team built physical hardware around components calibrated to replicate the thermal signature of the chip they were waiting for. That gives physical test data without requiring production silicon.

What Uberti is describing is, in effect, a systems engineering posture more common in aerospace or high-performance computing programs than in the typical AI chip startup. The pressure to compress timelines in those fields is intense enough that parallel workstreams are standard practice, with interface control documents and agreed-upon specifications substituting for the actual hardware until it arrives. Applying that discipline to a new AI accelerator program is a choice, not a given, and it implies a level of confidence in the chip’s specifications that has to be earned through modeling before it can be confirmed through measurement.

Whether the approach paid off in schedule terms is a question the available evidence does not settle. What Uberti’s account does establish is that Etched treated rack design as a first-class engineering problem from early in the program, not a detail to be resolved after the more glamorous work of chip design was complete. In a field where thermal and power delivery constraints are increasingly the binding limits on accelerator performance, that framing matters. A chip that arrives to a mature, tested rack is in a meaningfully different position than one that arrives to a blank slate. The time saved may be weeks or months, and in competitive AI infrastructure markets, either of those is consequential.